(a) Field of the Invention
This invention relates to the operation of a non volatile flash memory device and in particular to programming and erasing the device by manipulating the stored charge within.
(b) Description of the Related Art
A flash EEPROM device is a semiconductor device having non volatile memory properties which can be electrically programmed and erased. The non volatile memory properties enable the device to retain stored information once the power is turned off. The information is in the form of electrons stored within the floating gate. Devices of this type are described in U.S. Pat. Nos. 4,698,787 [1] and 5,077,691, [2] all of which are incorporated herein by reference. Other similar devices of this type are also described in U.S. Pat. Nos. 5,243,559, [3] 5,361,235, [4] 5,457,652, [5] 5,790,460 [6] and 5,572,464, [7] all of which are incorporated herein by reference.
Flash EEPROM devices are electrically erasable, programmable, read-only memory devices, which are electrically programmed and erased using on chip high and negative voltage generation circuitry. Data is stored in a binary format in the device in a manner that the device is set to a programmed state and reset to an erased state. Programming the device is accomplished by storing electrons in a floating gate or charge storing layer usually by means of tunneling or hot carrier injection. Erasing the device is done by removing the charge usually by means of tunneling.
In the prior art there are several programming and erase techniques for a flash memory mostly based on the physical phenomena of charge tunneling through a potential barrier. Implementation of tunneling erase techniques requires the usage of large electrical field across the dielectric between the floating gate and the well. These high electrical fields are known to generate reliability issues that degrade the quality of the dielectric which would eventually cause device failure. As devices advance further into sub micron dimensions, the intensity of the electric fields grow higher to become a dominating factor limiting the device scale down process.
Conventional flash device erase is achieved by application of a large negative voltage to the control gate and simultaneous application of a moderate positive voltage to the source region. This technique is usually referred to as Negative Gate Source Erase (NGSE). A variation to this method uses both source and drain regions in the erase process at the same time with the exact same bias operation methodology. FIG. 1 shows a prior art flash device using Fowler-Nordheim tunneling for NGSE. The device 9 is fabricated on a P-type substrate 10 which is maintained at ground potential, while a large negative potential Vg of about −11V is applied to the control gate 11 and simultaneously a positive potential Vs of about 5V is applied to the source region 12, fabricated from an n+ type semiconductor inside an n− region 15. The drain region 8 is kept floating throughout the process. The electrical field formed across the dielectric layer 19 between the floating gate and the substrate would yield a tunneling current draining the electrons stored in the floating gate.
This erase scheme suffers from a reliability issue caused by “hot hole” injection from the substrate 10 into the tunneling dielectric 19 [I-III]. Since the source region 16 is reversed biased during the erase operation, a band to band tunneling current is present at the surface 17. This tunneling current produces energetic holes that are attracted by the floating gate to source electric field and have a probability for tunneling into the floating gate. This probability is directly related to the magnitude of this electric field. Thus, the “hot hole” current has a strong dependency on the electric field and imposes yet another limit on device sizing as well as on operation voltage levels. The stronger the electric field the larger the tunneling current and vice versa. These “hot hole” cause damage to the semiconductor insulator interface 17 and the dielectric layer 19 by generating interface states and inter dielectric traps. Given enough time, these traps would line up to cause a breakdown of the insulator layer and rend the device useless, a phenomena known as Time Dependent Dielectric Breakdown (TDDB). TDDB theory presents an exponential dependency of the breakdown probability and time to failure of the device on the electrical field strength and stress duration. Attempting to prolong the time to failure by lowering the electric field would result in exponentially longer erase times since the Fowler-Nordheim tunneling current density has an inverse exponential dependency as well and would decrease with lower electric fields. Furthermore, by using NGSE the hot hole tunneling current is localized beneath the source and floating gate overlapping area and the likelihood of the dielectric traps to line up and form a breakthrough path is high.
Referring to FIG. 2, another prior art erase technique is presented using a p-type well structure 24. The p-well 24 is contacted using a p+ region 29 and formed in a deep n-type well 25. The n-well 25, which may be contacted using an n+ region 36, is formed within a p-type substrate 23. This erase technique uses a large negative bias potential Vg applied to the control gate 21 of about −11V while simultaneously applying a positive bias potential Vb of about 5V to the p-well 24 via the well terminal 29. The charge storing layer 28, also referred to as floating gate, lies beneath the control gate 21 with a dielectric 34 forming an intermediate insulating layer. Usually the p-type substrate 23 is grounded and the n-well 25 is kept floating during the erase operation. The source region 30 and the drain region 31 are either kept floating [3] or at the same potential as the p-well 24 [6], causing the electrons stored in the floating gate 28 to tunnel vertically 37 through the tunneling oxide 33 and into the channel region 22. This prior art erase technique is commonly referred to as Negative Gate Channel Erase (NGCE).
The NGCE technique suffers from a different reliability problem. Since the charge is erased into the channel region 22, by using high electric fields a high energy, a tunneling electron could impact ionize the semiconductor interface to generate an electron hole pair. This energetic hole, as in the previously presented NGSE method, would be attracted by the same high electric field and tunnel back through the dielectric layer 34 into the floating gate 28. This “hot hole” tunneling current would have the same affect on the dielectric quality and cause degradation over time. However, since in this case, the surface states and inter-dielectric traps are distributed along the entire channel length, most of the performance penalty would be manifested in device read current degradation and reduced programming performance. The impact on programming efficiencies results from the fact that these traps interfere with the hot carrier injection process.
Another prior art variation for NGCE technique [6] utilized the same biasing potential application for the p-type well 24 and the source region 30. This technique attempts to minimize the reliability problems induced by hot hole injection by applying the same potential bias to the source and the well, thus minimizing the band to band tunneling the would otherwise occur at the source dielectric interface 26. This prior art technique, however, does not eliminate the need for using high electric field across the dielectric during erase and the resulting TDDB and performance degradation issues.
FIG. 3 shows the biasing voltage waveform time dependence used to operate the flash device during erase in the prior art. All prior art techniques use an operation methodology that dictates a simultaneous application of the bias pulses for the control gate and the well either with or without the source and drain regions (the latter are either operated in the same manner as the well or kept floating). Since tunneling is the main mechanism used in erasing the device it is necessary to generate a strong electrical field over the dielectric during erase. As a result, the potential difference between the control gate and the well should be the highest obtainable. The well bias waveform has a finite rise and fall times and a positive polarity while the control gate bias waveform simultaneously assumes a negative polarity. The effective erase time for tunneling to occur is the actual overlap time of these two waveforms when the electric field is maximized. All prior art techniques attempt to maximize the overlap time between these waveforms in order to get the maximal electrical field during the erase sequence making them highly vulnerable to the above mentioned reliability issues. Another drawback of this prior art operation methodology is that the biasing scheme would also yield an electric field across the control gate to floating gate dielectric that would induce charge tunneling from the former to the latter. This tunneling current would interfere with the erase process by adding charge to the floating gate.
In the prior art there are several programming techniques for a flash memory based on the physical phenomena of charge tunneling through a potential barrier. Implementation of these Fowler-Nordheim tunneling based programming techniques requires the usage of large electrical field across the dielectric as for the erase case. Tunneling based programming is achieved simply by reversing the polarity of the applied bias to the control gate and source and well terminals, thus reversing the direction of the tunneling current. In particular by application of a large positive voltage to the control gate and simultaneous application of a moderate negative voltage to the well region. A variation to this method uses both source and drain regions along with the well region in the programming process at the same time with the exact same bias operation methodology. The merits of having a large electric field across the dielectric layer are inherent to the tunneling based programming scheme as for the tunneling based erase scheme.
Referring to FIG. 2, a prior art program technique is presented using a p-type well structure 24. The p-well 24 is contacted using a p+ region 29 and formed in a deep n-type well 25. The n-well 25, which may be contacted using an n+ region 36, is formed within a p-type substrate 23. This program technique uses a large positive bias potential Vg applied to the control gate 21 of about 10V [7] while simultaneously applying a positive bias potential Vb of about 10V to the p-well 24 via the well terminal 29. The source region 30 is grounded while the drain region 31 is kept floating or at the same potential as the source, causing the electrons from the source and drain to tunnel vertically 38 through the tunneling oxide 33 and into the floating gate 28.
When inter dielectric charge traps are present under the floating gate (as shown in FIG. 4 as 41b), the tunneling current from the floating gate to the well has two major components: the direct tunneling component (marked 37b as in FIG. 4) and the indirect tunneling component. The direct component is that of charge having sufficient energy to overcome the potential barrier and tunnel to the well, also commonly referred to as Fowler-Nordheim tunneling or “Field Emission”. The indirect component or trap assisted tunneling comprises of two stages. The first stage being the tunneling of charge from the floating gate to the trap (marked 38b in FIG. 4) and the second being tunneling of the same charge from the trap to the well (marked 39b in FIG. 4).
Application of high electric fields across the dielectric layer over time results in bond breaking in the dielectric molecular structures which serves as a charge trap. This trap, depending on its nature, can either capture a negative charge (i.e. electron) or a positive charge (i.e. hole). Given enough time these traps would align to form a conducting path from the floating gate to the source or substrate region. Once this occurs the device is considered to be broken down. The bond breaking process has a complex dependency on the applied electrical field stress time. In case the electric field is applied for a short period of time, some of the resulting traps are reversible in nature in a sense that the trapped charge will be released and the molecular bond will recover and remain intact after the removal of the stress. If the stress is applied for longer time periods, the broken bond is unrecoverable and a permanent trap is formed. Well known phenomena such as “Stress Induced Leakage Current” (SILC) [VI] and “Negative Bias Temperature Instability” (NBTI) [VII] may be explained by the reversible nature of these traps.
Dielectric film properties are modified as a result of trap generation as well, which in turn affects device performance. In the case of a silicon dioxide dielectric, “Anode Hydrogen Release” (AHI) [VIII] is a known phenomenon that results from electrical stress induced bond breaking and release of Hydrogen atoms. The Hydrogen is incorporated into the dielectric thin film during the manufacturing process in order to neutralize surface traps commonly referred to as “surface states”. Once the Hydrogen atoms are released from the surface, they migrate by means of diffusion through the dielectric layer and render its electrical properties as well as affecting the device's switching properties.
Dielectric trap generation of silicon (Si) based devices having silicon dioxide (SiO2) as a dielectric film has been widely investigated over the past decade. Trap generation as a result of the applied electric stress is commonly classified into two major categories [VIIII]. The first kind, referred to as surface traps ‘Nit’, caused by silicon-hydrogen bond breaking at the Si—SiO2 interface, resulting in hydrogen diffusion into the bulk oxide and having a partially recoverable nature. The second kind, referred to as oxide traps ‘Not’ (either at the bulk oxide or the interface), is the result of silicon:oxygen bond breaking and having a non recoverable nature. The non recoverable traps are caused by hot holes, created by Fowler-Nordheim stress during erase operation or impact ionization in the bulk Si during channel hot electron program operation, and injected into the dielectric layer. Minimizing the mechanisms of hot hole generation during device operation is a key factor in maximizing device reliability and lifetime.
High electric fields present between the control gate and the well are known to result in an unwanted leakage current between the floating gate and the control gate. This tunneling based leakage has an exponential dependence on the electric field and interferes both with program and erase of the device. Referring to FIG. 2, the charge tunneling between the control gate 21 and the floating gate 28 will always be in an opposite direction to the program or erase tunneling current and reduce the operation efficiency while increasing the overall power dissipation. Both FIGS. 3 and 5 demonstrate prior art operating methods which cause the above mentioned high electric fields. Referring to FIG. 3, a common prior art erase method waveform is depicted where the channel 22 is biased to a potential opposite to the stored charge 32 while the control gate 21 is biased to an opposite potential at the same time in order to allow the stored charge in the floating gate 28 to tunnel 37 to the channel. Referring to FIG. 5, a common prior art program method waveform is depicted where the control gate 21 is biased to a potential opposite to the stored charge 32 while the channel 22 is biased to an opposite potential at the same time in order to allow charge from the channel to tunnel into the floating gate 28. It is clear that the simultaneous application of opposite bias voltages across the dielectric layer 35 is the reason for these high electric fields. One prior art program and erase method that addresses the above mentioned issues is described in U.S. Pat. No. [8] 7,796,443, and having the operation voltage waveforms shown in FIGS. 7 and 8. Referring to FIGS. 7 and 8, the biasing voltage waveform time dependence used to operate the flash device during erase are shown. The well biasing voltage is of a positive polarity and the control gate biasing is of a negative polarity. By applying the first positive voltage to the well during the first stage, the inter dielectric and surface state traps would be forced to deplete from any stored charge within, while during the second stage, where the first bias is reset and the gate voltage inversely biased, charge is removed from the floating gate by direct and indirect, trap assisted, tunneling currents.
The background and associate prior art erase procedures are described in the following publications: [I] Witters, et al., “Degradation of Tunnel Oxide Floating Gate EPROM Devices and Correlation With High-Field-Current-Induced Degradation of Thin Gate Oxides”, IEEE Transactions On Electron Devices, Vol. 36, No. 9, September 1989, p. 1663. [II] Chun, et al., “Lateral Distribution of Erase Induced Hole Trapping and Interface Traps in Flash EPROM NMOSFET Devices”, IEEE Semiconductor Interface Specialists Conference, 1996. [III] A. Yokozawa, et al., “Investigation for Degradation of the Retention Characteristics due to Oxide Traps Induced by Hole Injection”, NVMSW proc. 1998 pp. 83-85. [IV] S. G. Dmitriev, Y. V. Markin, “Macroscopic Ion Traps at the Silicon Oxide Interface”, Semiconductor, Vol. 32, pp. 625-628, June 1988. [V] Vertoprakhov et al., “The effect of mobile charge in silicon dioxide on the surface states density of mos structure”, Russian Physical Journal, Vol. 19, pp. 378-379. [VI] Hu et al., “Stress induced current in thin silicon dioxide films”, IEDM '92. [VII] Kimizuka et al.“NBTI enhancement by nitrogen incorporation into ultrathin gate oxide”, symposium on VLSI 2000. [VIII] DiMaria et al., “Hydrogen Electrochemistry and Stress-Induced Leakage Current in Silica,” PRL. 83, (1999). [VIIII] Mahapatra et al., “On the Generation and Recovery of Interface Traps in MOSFETs Subjected to NBTI, FN and HCI stress”, IEEE Trans. On Elect. Devices, July 2006.